(1) Field of the Invention
The invention relates to a method of metallization in the fabrication of integrated circuits, and more particularly, to a method of forming dummy structures at the corners of the die thereby preventing stress-induced cracking at the corners of the die in the manufacture of integrated circuits.
(2) Description of the Prior Art
After semiconductor device fabrication has been completed on a wafer, the wafer is separated into individual integrated circuit chips. During singulation, or wafer sawing, mechanical damage may occur, resulting in chipping or delamination. These chips can act as nucleation sites for stress-induced cracking. The cracks can then propagate into the die and eventually cause failure of the circuitry, especially after temperature excursions. The delamination can result in separation of the die layers and result in contaminant, usually moisture, incursion and eventually device failure.
To reduce RC delay, the copper damascene process has been implemented along with low dielectric constant (k) dielectric material. Due to the thermal mis-match between the low-k material and silicon, physical considerations such as adhesion, stress, and shear become crucial for advanced technology. During packaging, the corners of the die exhibit high stress and tend to crack. Therefore, it is important to fabricate some dummy structures to prevent delamination and crack propagation even for flip-chip and bump products.
U.S. Pat. No. 4,928,162 to Lesk et al discloses formation of dummy metal topographical configurations at the corners of a semiconductor die in order to prevent cracking and delamination at the corners. U.S. Pat. No. 6,022,792 to Ishii et al teaches forming dummy bump electrodes around the periphery of a substrate. U.S. Pat. No. 6,479,887 to Yoon et al shows a circuit pattern tape including dummy structures.